A high speed analog VLSI image acquisition
and low-level image processing system is presented. The
architecture of the chip is based on a dynamically reconfigurable
SIMD processor array. The chip features a massively
parallel architecture enabling the computation of
programmable mask-based image processing in each pixel.
Each pixel include a photodiode, an amplifier, two storage
capacitors, and an analog arithmetic unit based on a fourquadrant
multiplier architecture. A 64 9 64 pixel proof-ofconcept
chip was fabricated in a 0.35 lm standard CMOS
process, with a pixel size of 35 lm 9 35 lm. The chip can
capture raw images up to 10,000 fps and runs low-level
image processing at a framerate of 2,000–5,000 fps.